I am a PhD student in the Electrical Engineering department at Stanford University.
- 2013, MS, Electrical Engineering, Stanford University
- 2011, BS, Electrical and Computer Engineering, Carnegie Mellon University
I am part of the Robust Systems Group at Stanford.
My research deals with cross-layer resilience, self-repair, and recovery of reliable systems.
At CMU, I worked as a student researcher on the Claytronics Project.
E. Cheng, S. Mirkhani, L. G. Szafaryn, C.-Y. Cher, H. Cho, K. Skadron, M. R. Stan, K. Lilja, J. A. Abraham, P. Bose, and S. Mitra,
"CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores,"
Design Automation Conference, 2016.
(ACM, IEEE, pdf)
S. Mitra, P. Bose, E. Cheng, H. Cho, R. Joshi, Y. M. Kim, C. R. Lefurgy, Y. Li, K. P. Rodbell, K. Skadron, J. Stathis, and L. Szafaryn,
"The Resilience Wall: Cross-Layer Solution Strategies,"
International Symposium on VLSI Technology, Systems, and Applications, 2014.
Y. Li, E. Cheng, S. Makar, and S. Mitra,
"Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study,"
International Test Conference, 2013.
- Silicon Errors in Logic - System Effects (SELSE), 2016 (selected for Best of SELSE session at DSN)
- Highly-Reliable Power-Efficient Embedded Designs (HARSH), 2016 (awarded Best Paper)
- Resiliency in Embedded Electronic Systems (REES), 2015
- Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2015
- Silicon Errors in Logic - System Effects (SELSE), 2013
- Assisted Program Chair: International Test Conference (ITC), 2014 (awarded Gerry Gordon Student Volunteer Award)
- Reviewer: ACM Computing Surveys, Microelectronics Reliability, Proceedings of the IEEE, International Conference on Computer Aided Design (ICCAD), International Test Conference (ITC)
I have interned at the following companies:
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