Research
At Stanford, I was part of the Robust Systems Group where I worked on cross-layer resilience, self-repair, and recovery of reliable systems.
At CMU, I worked as a student researcher on the Claytronics Project.
Publications:
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E. Cheng and S. J. B. Yoo,
"Cacheless Computer Architectures: 3D Integration of Optical Interconnects and Novel Memory,"
The Next Wave, 2022.
(GPO, pdf)
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D. Mueller-Gritschneder, E. Cheng, U. Sharif, V. Kleeberger, P. Bose, S. Mitra, and U. Schlichtmann,
"Cross-Layer Resilience Against Soft Errors: Key Insights,"
Dependable Embedded Systems, Springer, 2021.
(Springer, pdf)
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E. Cheng and S. Mitra,
"Cross-Layer Resilience,"
Cross-Layer Reliability of Computing Systems, The Institution of Engineering and Technology, 2020.
(IET, pdf)
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E. Cheng, D. Mueller-Gritschneder, J. Abraham, P. Bose, A. Buyuktosunoglu, D. Chen, H. Cho, Y. Li, U. Sharif, K. Skadron, M. Stan, U. Schlichtmann, S. Mitra,
"Cross-Layer Resilience: Challenges, Insights, and the Road Ahead,"
Design Automation Conference, 2019.
(ACM, IEEE, pdf)
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E. Cheng, S. Mirkhani, L. G. Szafaryn, C.-Y. Cher, H. Cho, K. Skadron, M. R. Stan, K. Lilja, J. A. Abraham, P. Bose, and S. Mitra,
"Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience),"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
(IEEE, pdf)
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D. Mueller-Gritschneder, M. Dittrich, J. Weinzierl, E. Cheng, S. Mitra, and U. Schlichtmann,
"ETISS-ML: A Multi-Level Instruction Set Simulator with RTL-level Fault Injection Support for the Evaluation of Cross-Layer Resiliency Techniques,"
Design, Automation and Test in Europe, 2018.
(IEEE, pdf)
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E. Cheng, J. Abraham, P. Bose, A. Buyuktosunoglu, K. Campbell, D. Chen, C.-Y. Cher, H. Cho, B. Le, K. Lilja, S. Mirkhani, K. Skadron, M. Stan, L. Szafaryn, C. Vezyrtzis, and S. Mitra,
"Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights,"
International Conference on Computer Design, 2017.
(IEEE, pdf)
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R. Bertran, P. Bose, D. Brooks, J. Burns, A. Buyuktosunoglu, N. Chandramoorthy, E. Cheng, M. Cochet, S. Eldridge, D. Friedman, H. Jacobson, R. Joshi, S. Mitra, R. Montoye, A. Paidimarri, P. Parida, K. Skadron, M. Stan, K. Swaminathan, A. Vega, S. Venkataramani, C. Vezyrtzis, G.-Y. Wei, J.-D. Wellman, and M. Ziegler,
"Very Low Voltage (VLV) Design,"
International Conference on Computer Design, 2017.
(IEEE, pdf)
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H. Cho, E. Cheng, T. Shepherd, C.-Y. Cher, and S. Mitra,
"System-Level Effects of Soft Errors in Uncore Components,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017.
(IEEE, pdf)
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E. Cheng and S. Mitra,
"Resilience in Next-Generation Embedded Systems,"
Rugged Embedded Systems: Computing in Harsh Environments, Morgan Kaufmann, 2016.
(Elsevier, pdf)
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E. Cheng, S. Mirkhani, L. G. Szafaryn, C.-Y. Cher, H. Cho, K. Skadron, M. R. Stan, K. Lilja, J. A. Abraham, P. Bose, and S. Mitra,
"CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores,"
Design Automation Conference, 2016.
(ACM, IEEE, pdf)
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S. Mitra, P. Bose, E. Cheng, H. Cho, R. Joshi, Y. M. Kim, C. R. Lefurgy, Y. Li, K. P. Rodbell, K. Skadron, J. Stathis, and L. Szafaryn,
"The Resilience Wall: Cross-Layer Solution Strategies,"
International Symposium on VLSI Technology, Systems, and Applications, 2014.
(IEEE, pdf)
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Y. Li, E. Cheng, S. Makar, and S. Mitra,
"Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study,"
International Test Conference, 2013.
(IEEE, pdf)
Workshop Papers / Special Presentations:
- Top Picks in Test and Reliability, 2023
- Salishan Conference on High Speed Computing, 2022
- Irregular Applications: Architectures and Algorithms (IA3), 2021
- CRNCH Summit, 2021
- Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2017, 2015
- Semiconductor Research Corporation (SRC) TECHCON, 2016
- International Conference on Dependable Systems and Networks (DSN), 2016 (Best of SELSE special session)
- Silicon Errors in Logic - System Effects (SELSE), 2016 (selected for Best of SELSE session at DSN), 2013
- Highly-Reliable Power-Efficient Embedded Designs (HARSH), 2016 (awarded Best Paper)
- Resiliency in Embedded Electronic Systems (REES), 2015
Professional Service:
- Program Committee:
The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC),
Workshop on Irregular Applications: Architectures and Algorithms (IA3)
- Reviewer:
ACM Computing Surveys,
ACM Transactions on Design Automation of Electronic Systems (TODAES),
IEEE Design & Test,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),
IEEE Transactions on Computers,
IEEE Transactions on Emerging Topics in Computing (TETC),
Microelectronics Reliability,
Proceedings of the IEEE,
International Conference on Computer Aided Design (ICCAD),
International Test Conference (ITC)
- Assisted Program Chair: International Test Conference (ITC), 2014 (awarded Gerry Gordon Student Volunteer Award)
Work Experience
I have interned at the following companies:
Last modified: May 12, 2024